Simulation and Analysis of Propagation Delay and Power Dissipation in CMOS Inverter on CADENCE Virtuoso

Abstract

This study presents a comparative study of propagation delay and power dissipation in CMOS inverters. Since power consumption is a critical design constraint in low-power VLSI systems, the Propagation Delay Product provides a valuable metric for evaluating overall circuit efficiency. The research investigates how transistor width-to-length ratios, capacitive loading, and temperature variations influence inverter characteristics. the stack approach on the propagation delay and dynamic power dissipation of CMOS inverter. Simulations were conducted using CADENCE tools to analyze circuit performance. using gpdk 90 nm technology and several techniques.