Quantification of the effects of Si3N4 gate thickness on the enhancement of a-Si:H thin film transistor performances

Abstract

To improve the performance of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), which are used in flat-panel displays and related electronic devices, we investigated the effect of reducing the Si 3 N 4 gate-insulator thickness ( d i ) on selected transistor parameters ( P ). Two-dimensional numerical simulations were performed using Atlas-Silvaco. As d i decreased from 300 to 15 nm, the a-Si:H TFTs showed sharper switching behavior, with the drain current increasing from an off-state current (I off ) of 1.4 × 10 −12 A to an on-state current ( I on ) of approximately 1.8 × 10 −5 A at low operating voltages. For d i = 15 nm, the extracted parameters were a threshold voltage ( V th ) of 3.06 V, field-effect mobility ( μ FE ) of approximately 0.037 cm 2 V −1 s -1 , subthreshold swing ( SS ) of 0.10 V dec −1 , gate capacitance per unit area ( C i ) of 44.25 × 10 −8 F cm -2 , and maximum electric field ( E max ) of 1.65 × 10 5 V cm -1 . As d i decreased, C i , I on , I on / I off , and E max increased, whereas V th , μ FE , I off , and SS decreased. These trends were quantified by curve fitting to obtain empirical P = f ( d i ) relations for each parameter. The fitted relations provide a practical basis for estimating the Si 3 N 4 gate-insulator thickness required to target specific electrical parameters in a-Si:H TFT design.