Pipelined FPGA Architecture for LST Split-Window Algorithm with Optimized Hardware Resource Usage

Abstract

FPGAs are becoming an essential hardware component in satellite remote sensing because they enable realtime processing of massive volumes of data captured by onboard sensors, while meeting strict constraints of energy, reliability, and radiation in space. Their ability to be reconfigured and processed in parallel is ideal for implementing complex algorithms, such as the Land Surface Temperature-Split Window algorithm, directly onboard the satellite. This research paper presents a new optimized implementation of the LST-SW algorithm based on a radiation FPGA. The use of VHDL and optimized architecture, such as pipelining and DSP/BRAM resource sharing, reduces the material consumption while enabling maximum frequency. This approach improves calculation throughput and enables near real-time processing, which is essential for embedded applications. By integrating parallel tasks within a structured pipeline design, the algorithm becomes more efficient than the usual methods. This solution constitutes a key advance for on-board satellite systems requiring speed and the less hardware resources consumed.