Low-Power Design of a 3 Gbps LVDS Receiver for Optical Data Transmission

Abstract

This paper presents a design methodology of high speed, low power, 3Gbits/s, CMOS differential receiver. The latter is designed for the integration in a demultiplexer chip, named Demux1, which is a building block of an aperture plate system (APS) that is part of a projection maskless lithography (PML2) tool. The receiver gets at its inputs the lowvoltage differential signals (LVDS) and recovers the data as a single ended signal at its output. It is implemented using a comparator and an adaptable delay chain with a resolution of 20 ps to compensate for input channels skew. This solution avoids the use of very power consuming PLLs, and is highly configurable to allow situation dependent error reporting. Being produced in a United Microelectronics Corporation (UMC, Taiwan) <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18 \mu \mathrm{m}$</tex> CMOS process using 1-poly and 5metal layers, it has a wide input range compared with conventional receivers, a total power consumption of about 3.5 mW, a temperature range of 20 to 125 °C and an operating voltage of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.8 \mathrm{V} (\pm 10 \%)$</tex>.