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Fault-Tolerant FPGA-Based System for Mitigating SEUs in Configuration and User Bits

Abstract

This paper addresses two issues. First, in the context of factory automation, a low-cost fault-tolerant sensor system is proposed along with its FPGA-based voter. Second, the voter itself is designed to recover from failures affecting its own circuitry. The sensor system consists of one high-quality sensor used for measurement along with two functionally identical, but lower cost sensors used for monitoring purposes. A biased voter circuit is designed and implemented on the same Field Programmable Gate Array (FPGA) used to house the controller. It is shown that the voter can detect and recover from Single Event Upsets (SEUs) which often occur in the harsh factory environments. Both FPGA configuration and user bits are protected. It was shown that the proposed design requires less resources and power than some other designs presented in the literature. Focusing next on recovering from SEUs in both user and configuration FPGA bits, another use case is investigated, namely an I2C master; it is shown that the proposed design again requires less resources than some other commonly used techniques. Both proposed designs were implemented on the Xilinx Zynq-7000 (xc7z020clg400-1).

Research topics

  • Embedded Systems Design Techniques

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DOI: 10.1109/icm63406.2024.10815856

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