MARATTO

article

Cycle Slipping Cancellation in Bang-Bang PLLs

Abstract

Digital phase-locked loops (DPLLs) based on bang-bang phase detectors (BBPD) are now very common in many communication systems specially in clock and data recovery. However, it suffers from long settling time due to cycle slipping issue and even at some point it fails to achieve lock. This paper presents a simple and efficient technique to resolve the issue of locking failure in bang-bang phase-locked loops (BBPLL) by detecting the instants of cycle slipping and cancelling its effect. Simulation results show that locking is achieved with the proposed cycle slipping cancellation (CSC) technique for cases at which the conventional BBPLL fails to achieve lock.

Research topics

  • Advancements in PLL and VCO Technologies
  • Photonic and Optical Devices
  • Electromagnetic Compatibility and Noise Suppression

Read the original research

This page summarises published work. The authoritative version sits with the publisher.

DOI: 10.1109/niles63360.2024.10753256

Is something wrong with this record? Report it or request removal.

Discussion

Discuss this research

Have you built on this work, tried to replicate it, or seen it applied in practice? Share what you know. Verified researchers and MARATTO™ domain experts can open a discussion, and any member can reply. Contributions are reviewed before they appear.

No discussion yet. Open the first thread.