article · Results in Engineering
Low power, compact dimensions, and energy efficiency are critical requirements for the success of internet of things systems. Approximate computing offers a viable method to deliver high performance and energy savings in computationally intense applications that can tolerate minor errors. To address this need, an inexact reverse carry select adder with back carry propagation has been developed. The concept features three separate design variations, with back carry propagation applied across 16-bit ripple carry adders and 16-bit carry select adders. The designs were implemented using CADENCE schematic tools and simulated in a 45 nm CMOS process. Evaluations against existing back carry propagate full adders demonstrated notable performance gains. In particular, the third variant cut power use by 34.84 per cent and reduced delay by 56.91 per cent compared to traditional carry select adders, while achieving substantial energy reductions compared to conventional ripple carry and carry select designs.
Connected internet of things devices rely on compact microchips that consume minimal electrical power to prolong battery life. By accepting minor calculation approximations in tasks that can tolerate them, these adder designs sharply reduce energy consumption and operating delays. This allows electronic systems to process intensive data faster while using significantly less power.
This work is relevant to semiconductor developers and circuit designers building low-power hardware for internet of things systems and error-tolerant computing tasks. Evaluated through CADENCE schematic simulations on 45 nm CMOS technology, the research is at an applied simulation and design stage, requiring physical fabrication and silicon testing before it can reach commercial deployment.
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Low cost, low form factor and highly energy efficient VLSI design is the key for the success of internet of things (IoT) paradigm. Approximate computing is one of the major techniques used to achieve high performance and energy efficiency in error resistant computationally intense applications. Low power VLSI design is one of the important factors in the designing of new IoT system or reconstructing the existed IoT system. An inexact reverse carry select adder (IRCSLA) with back carry propagation is presented in this work. Three different types of adder implementations were presented in IRCSLA. The method of back carry propagation is applied to the design of both 16-bit ripple carry adder (RCA) & 16-bit carry select adders. These adders were designed in CADENCE schematic tool and simulations were done in Analog Design Environment with 45 nm CMOS technology. The design parameters such as delay and power of the three IRCSLA designs were compared with the existed back carry propagate full adders. IRCSLA-III gives 34.84% reduction in power and 56.91% improvement in delay compared to conventional CSLA adder and also improves the energy at the rate of 86.77% and 71.92% compared to the conventional RCA and a CSLA adder respectively.
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DOI: 10.1016/j.rineng.2023.101127
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