A Cascaded H-Bridge Multilevel Inverter with DC Cells Input Fault Tolerance Capability Based on PSC-PWM Control

Abstract

Multilevel inverters have proven their efficiency in generating better AC voltage outputs. This functional quality is mainly due to the use of multi-source DC inputs. Despite the fact that this type of topology is generally reliable, switching faults caused by the complete loss of a switching component or DC input cell may still occur. Such incident may inflict heavy impacts to the conversion chain resulting in a permanent damage to the switching cells or the connected load. This article presents a dynamic switching control strategy capable of tolerating DC cells open-circuit input faults in basic symmetric Cascaded H-bridge multilevel inverter architectures. The proposed topology uses a control scheme to overcome the switching cells’ fault by adapting the configured level of conversion and bypassing the flawed unit with no additional switching components. Furthermore, the proposed control strategy is capable of reversing back the inverter configuration to its original functional state after the disappearance of the faut. This research article answers the need for a theorical study of a fault tolerant Cascaded H-Bridge multilevel inverter where the short circuit’s fault types are bypassed by Pulse width modulation alteration only.